The present invention relates, in general, to an asynchronous sample rate converter, and more particularly, to a method for fast tracking and jitter improvement in an asynchronous sample rate converter.
In some particular applications of digital signal processing, there is a need to change a sampling rate of a signal, either increasing it or decreasing it. For example, in telecommunication systems that transmit and receive different types of signals (e.g., facsimile, speech, video), various signals must be processed at different rates depending on corresponding bandwidths. The process of converting a signal from a given rate to a different rate is called sample rate conversion. In some applications where the input and output samples are controlled by independent clocks, this process is known as asynchronous sample rate conversion. An overview of sample rate conversion techniques can be found in “Digital Signal Processing” by J. Proakis and D. Manolakis (third edition, Prentice Hall, 1996).
For example, with respect to some applications, there is a requirement to include a module called an “asynchronous sample rate conversion (ASRC)” in a processor such as a digital signal processor (DSP). This module is used, for example, to convert an audio data stream from one sampling rate to another sampling rate. The ASRC module is characterized mainly by a response time, and Signal-to-Noise-Distortion-Ratio (SNDR) after conversion.
One important element influencing the final ASRC SNDR performance is the ratio Fsin/Fsout between the input sampling rate Fsin and the output sampling rate Fsout, where a fast convergence time and low jitter are desirable. Slow convergence can cause buffer under-run or over-run, and jitter can degrade the final SNDR performance.
Patent document WO2003/081774A1 discloses a digital phase locked loop (DPLL) for an asynchronous sample rate conversion. This DPLL can track the ratio Fsin/Fsout.
FIG. 1 is a schematic block diagram of a conventional asynchronous sample rate conversion (ASRC) digital phase locked loop (DPLL). As shown in FIG. 1, the conventional ASRC DPLL includes two branches, i.e., an input counter 101 and a system counter 104, which respectively perform first and second processing.
A first processing unit, which performs the first processing, includes: an input counter 101 that performs a control based on an input clock; a first latch 102 that has an input receiving an output of the input counter 101, performs a control based on an output clock, latches a first input signal when the output clock is asserted, and outputs a first processed input signal.
A second processing unit, which performs the second processing, includes: a system counter 104 that performs a control based on a DSP system clock and is reset by an input clock; a second latch 109, similar to the first latch 102, that has an input receiving an output of the system counter 104, performs a control based on an output clock, and latches a second input signal when the output clock is asserted; a third latch 105 that has an input receiving the output of the system counter 104 and performs a control based on an input clock; a fourth clock 106 that has an input receiving an output of the third latch 105, performs a control based on an output clock, and latches the input signal when the output clock is asserted; and a division module 107 that receives an output signal x of the second latch 109 and an output signal y of the forth latch 106 and performs a division of the two output signals to thereby output a second processed input signal.
The first processed input signal and the second processed input signal are summed in a first summer 103, and the summed signal, i.e., a summed input signal C, is output to a subtractor 108. In the subtractor 108, a feedback signal is subtracted (the generation of the feedback signal will be described later) from the summed input signal C, thereby obtaining a predicted input signal (i.e., error signal) E.
The output of the subtractor, i.e., the predicted input signal (error signal) E, is input to two gain amplifiers 113 and 114, respectively. The amplified gain of the first gain amplifier 113 is Ki, and the amplified gain of the second gain 114 amplifier is Kp. According to the predicted input signal, a gain controller 115 controls the two gain amplifiers 113 and 114, respectively.
The predicted input signal E enters a first integrator 111 after being amplified by the gain amplifier 113 and a first integrated signal is output from the first integrator 111. The predicted input signal E and the first integrated signal are summed in a second summer 110 after the predicted input signal E is amplified by the gain amplifier 114 and a summed amplified signal R is generated from the second summer 110. The summed amplified signal R is output via a second integrator 112 as an integer part n0 and a fractional part f. The second integrator 112 is controlled under the output clock, and an output of the second integrator returns to the subtractor 108 as the mentioned feedback signal. Recall that the predicted input signal (error signal) E is obtained by subtracting said feedback signal from the summed input signal C.
However, if the implementation disclosed in this patent document is used, when the input sampling rate is very near the output sampling rate, the SNDR performance is only low at 90 dB, and it cannot reach 120 dB as desired. More particularly, it can be seen from FIG. 1 that the input data for the DPLL are derived from the input counter 101 and the system counter 104 and pass through latches 102, 109, and 106. However, the outputs from the latches 109 and 106 are not from the same input clock interval. As the counters 101 and 104 are quantized elements, a quantized error needs to be carefully dealt with. From the real-time implementation, misalignment in time of the output from the latches 109 and 106 can amplify the quantization error, and causes great jitter to the input of DPLL, which reduces the SNDR performance.